1. Field of the Invention
The present invention relates to a printed circuit board layout.
2. Background Information
Integrated circuits are typically assembled into packages that are soldered to a printed circuit board. The packages and printed circuit board may be part of an electrical system such as a computer.
The printed circuit board contains routing traces that interconnect a plurality of integrated circuit packages that are mounted to the board. The routing traces typically carry digital signals that are transmitted between the integrated circuits of the system.
Some integrated circuits have a relatively large number of input/output (I/O) pads. The large number of I/O pads require a larger number of routing traces. Some printed circuit boards require multiple layers of routing traces to accommodate all of the I/O for the system. Routing traces located within different layers are typically connected by vias formed in the board. Multiple layers and interconnecting vias increase the complexity and cost of constructing the circuit board.
The integrated circuit packages typically have leads that are soldered to corresponding contact pads of the printed circuit board. The leads of some integrated circuit packages are aligned in a pair of single rows that extend along opposite sides of the package. One type of dual row package is referred to as a TSOP package. The top surface of the printed circuit board typically contains routing traces that route the contact pads to a row(s) of vias located on each side of the package. Such an arrangement simplifies the routing of the printed circuit board but limits the I/O of the package.
There have been developed integrated circuit packages which have a two-dimensional array of contacts located along a bottom surface of the package. For example there have been developed integrated circuit packages which contain a two-dimensional array of external solder balls that are reflowed onto the printed circuit board. These types of packages are typically referred to as ball grid array (BGA) packages.
It is difficult to route a two-dimensional array of contacts, particularly the contacts located at the center of the array. Routing two-dimensional arrays typically requires multiple routing layers. Each routing layer increases the cost of producing the printed circuit board. It would be desirable to provide a printed circuit board layout that effectively routes a two-dimensional array of contacts to an array of vias that extends along one edge of the package similar to a via array(s) used with TSOP packages.